n25q256 Numonyx, n25q256 Datasheet - Page 78

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n25q256

Manufacturer Part Number
n25q256
Description
256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
Manufacturer
Numonyx
Datasheet

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Instructions
9.1.13
Note:
78/186
DQ0
DQ1
DQ3
DQ2
C
S
Mode 3
Mode 0
Quad I/O Fast Read
The Quad I/O Fast Read (QIOFR) instruction is very similar to the Quad Output Fast Read
(QOFR), except that the address bits are shifted in on four pins (pin DQ0, pin DQ1, pin
W/VPP/DQ2 and pin HOLD/DQ3 (1)) instead of only one.
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
Reset functionality is available instead of Hold in devices with a dedicated part number. See
Section 16: Ordering
Figure 30. Quad Input/Output Fast Read instruction sequence
0
‘1’
Don’t Care
Don’t Care
1
Section 5.1.2: 4 Byte Address Mode on page 25
2
Instruction
3
4
5
information.
6
7
20 16 12 8
21 17 13 9
22 18 14 10
23 19 15 11
8
24-bit Address
9 10 11 12 13 14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
6
7
4
5
0
1
2
3
Dummy (ex.: 10)
15 16
21 22 23
©2010 Micron Technology, Inc. All rights reserved.
Byte 1
24
6
7
4
5
IO switches from Input to Output
25
1
2
3
0
26
Byte 2
6
7
4
5
27
2
3
0
1
N25Q256 - 3 V
6
7
4
5

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