n25q256 Numonyx, n25q256 Datasheet - Page 34

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Operating features
5.4.4
5.4.5
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Similar to the Extended SPI protocol in the QIO-SPI protocol, to program one data byte two
instructions are required:
This is followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Quad Command Page Program (QCPP) instruction allows up
to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they are
in consecutive addresses on the same page of memory.
For optimized timings, it is recommended to use the QCPP instruction to program all
consecutive targeted bytes in a single sequence versus using several QCPP sequences
with each containing only a few bytes. See
The QCPP instruction is transmitted across 4 data lines except when VPP is raised to
VPPH.
The VPP can be raised to VPPH to decrease programming time (provided that the bit 3 of
the VECR has been set to 0 in advance). When bit 3 of VECR is set to 0 after the Quad
Command Page Program instruction sequence has been received, the memory temporarily
goes in Extended SPI protocol, and is possible to perform polling instructions (checking the
WIP bit of the Status Register or the Program/Erase Controller bit of the Flag Status
Register) or Program/Erase Suspend instruction even if DQ2 is temporarily used in this VPP
functionality. The memory automatically comes back in QIO-SPI protocol as soon as the
VPP pin goes Low.
Subsector Erase, Sector Erase, and Bulk Erase
Similar to the Extended SPI protocol, Subsector Erase (SSE), the Sector Erase (SE) and
the Bulk Erase (BE) instructions are used to erase the memory in the QIO-SPI protocol.
These instructions start an internal Erase cycle (of duration tSSE, tSE or tBE).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
The erase instructions are transmitted across 4 data lines unless the VPP is raised to
VPPH.
The VPP can be raised to VPPH to decrease erasing time, provided that the bit 3 of the
VECR has been set to 0 in advance. In this case, after the erase instruction sequence has
been received, the memory temporarily goes in extended SPI protocol, and it is possible to
perform polling instructions (checking the WIP bit of the Status Register or the
Program/Erase Controller bit of the Flag Status Register) or Program/Erase Suspend
instruction even if DQ2 is temporarily used in this VPP functionality. The memory
automatically comes back in QIO-SPI protocol as soon as the VPP pin goes Low.
Polling during a Write, Program, or Erase cycle
It is possible to check if the internal write, program or erase operation is completed, by
polling the dedicated register bits of the Read Status Register (RDSR) or Read Flag Status
Register (FSR).
When the Program or Erase cycle is performed with the VPP, the device temporarily goes in
single I/O SPI mode. The protocol became again QIO-SPI as soon as the VPP pin voltage
goes low.
Write Enable (WREN), which is one byte, and
Quad Command Page Program (QCPP) sequence, which consists of instruction (one
byte), address (3 bytes) and input data.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Table 34.: AC
Characteristics.
©2010 Micron Technology, Inc. All rights reserved.
N25Q256 - 3 V