n25q256 Numonyx, n25q256 Datasheet - Page 60

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Instructions
9
Note:
9.1
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Instructions
The device can work in three different protocols: Extended SPI, DIO-SPI and QIO-SPI.
Each protocol has a dedicated instruction set, and each instruction set features the same
functionality:
The application can choose in every time of the device life which protocol to use by setting
the dedicated bits either in the Non Volatile Configuration Register or the Volatile Enhanced
Configuration Register.
In multiple SPI protocols, all instructions, addresses, and data are parallel on two lines (DIO-
SPI protocol) or four lines (QIO-SPI protocol).
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial Data input(s) is (are) sampled on the first rising edge of Serial Clock (C) after Chip
Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the
device, most significant bit first, on Serial Data input(s), each bit being latched on the rising
edges of Serial Clock (C). Instruction code is shifted into the device just on DQ0 in Extended
SPI protocol, on DQ0 and DQ1 in DIO-SPI protocol and on DQ0, DQ1, DQ2, and DQ3 in
QIO-SPI protocol.
In standard mode every instruction sequence starts with a one-byte instruction code.
Depending on the instruction, this might be followed by address bytes, or by data bytes, or
by both or none.
In XIP modes only read operation and exit XIP mode can be performed, and to read the
memory content no instructions code are needed: the device directly receives addresses
and after a configurable number of dummy clock cycle it outputs the required data.
Extended SPI Instructions
In Extended SPI protocol instruction set the instruction code is always shifted into the device
just on DQ0 pin, while depending on the instruction addresses and input/output data can run
on single, two or four wires.
In the case of a Read Instructions Data Bytes (READ), Read Data Bytes using 4 bytes
address (READ4BYTE), Read Data Bytes at Higher Speed (FAST_READ), Read Data
Bytes using 4 bytes at Higher Speed s(FAST_READ4BYTE), Dual Output Fast Read
(DOFR), Dual Output Fast Read using 4 bytes address (DOFR4BYTE), Dual Input/Output
Fast Read (DIOFR), Dual Input/Output Fast Read using 4 bytes address (DIOFR4BYTE),
Quad Output Fast Read (QOFR), Quad Output Fast Read using 4 bytes address
(QOFR4BYTE), Quad Input/Output Fast Read (QIOFR), Quad Input/Output Fast Read
using 4 bytes address (QIOFR4BYTE), Read OTP (ROTP), Read Lock Registers (RDLR),
Read Status Register (RDSR), Read Flag Status Register (RFSR), Read NV Configuration
Register (RDNVCR), Read Volatile Configuration Register (RDVCR), Read Volatile
Read, program and erase the memory and the 64 byte OTP area,
Suspend and resume the program or erase operations,
Read and modify all the registers and to read the device ID: please note that in this
case there is a small functionality difference among the single and the multiple I/O read
ID instructions. See
Section 9.3.1: Multiple I/O Read Identification
Section 9.2.1: Multiple I/O Read Identification protocol
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(MIORDID).
©2010 Micron Technology, Inc. All rights reserved.
N25Q256 - 3 V
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