n25q256 Numonyx, n25q256 Datasheet - Page 47

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
6.4.2
6.4.3
Note:
6.4.4
(WRVECR) instruction. The default value of this bit is 1, corresponding to Extended SPI
protocol, If this bit is set to 0 the memory works in QIO-SPI protocol. If VECR bit 7 is set
back to 1 the memory start working again in Extended SPI protocol, unless the bit 6 is set to
0 (in this case the memory start working in DIO-SPI mode).
Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 7and bit 6 of the
VECR set to 0), the memory will work in QIO-SPI.
Dual Input Command VECR<6>
The Dual Input Command configuration bit can be used to make the memory start working
in DIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register
(WVECR) instruction. The default value of this bit is 1, corresponding to Extended SPI
protocol, if this bit is set to 0 the memory works in DIO-SPI protocol (unless the Volatile
Enhanced Configuration Register bit 7 is also set to 0). If the Volatile Enhanced
Configuration Register bit 6 is set back to 1 the memory start working again in Extended SPI
protocol.
Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 7 and bit 6 of the
VECR are set to 0), the memory will work in QIO-SPI.
Reset/Hold disable VECR<4>
The Hold (RESET) disable bit can be used to disable the Hold (Reset) functionality of the
Hold (Reset) / DQ3 pin right after the Write Volatile Enhanced Configuration Register
(WVECR) instruction. This feature can be useful to avoid accidental Hold or Reset condition
entries in applications that never require the Hold (Reset) functionality. If this bit is set to 0
the Hold (Reset) functionality is disabled, it is possible to enable it back by setting this bit to
1.
Please note that after the next power on the Hold (Reset) functionality will be enabled again
unless the bit 4 of the Non Volatile Configuration Register is set to 0.
Reset functionality is available instead of Hold in devices with a dedicated part number. See
Section 16: Ordering
Accelerator pin enable: QIO-SPI protocol / QIFP/QIEFP VECR<3>
The bit 3 of the Volatile Enhanced Configuration Register determine whether is possible or
not to use the Vpp accelerating voltage to speed up internal modify operation with Quad
program and erase instructions (both in Extended or QIO-SPI protocols).
If we want to use the Vpp voltage with Quad I/O modify instructions, we must set previously
this bit to 0 (his default value is 1, in this case the Vpp pin functionality is disabled in all
Quad I/O operations: both in Extended SPI and QIO-SPI protocols).
If the Volatile Enhanced Configuration Register bit 3 is set to 0, using the QIO-SPI protocol,
after a Quad Command Page Program instruction or an Erase instruction is received (with
all input data in the Program case) and the memory is de-selected, the protocol temporarily
switches to Extended SPI protocol until Vpp passes from Vpph to normal I/O value (this
transition is mandatory to come back to QIO-SPI protocol), to enable the possibility to
perform polling instructions (to check if the internal modify cycle is finished by means of the
WIP bit of the Status Register or of the Program/Erase controller bit of the Flag Status
register) or Program/Erase Suspend instruction even if the DQ2 pin is temporarily used in
his Vpp functionality.
information.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Volatile and Non Volatile Registers
©2010 Micron Technology, Inc. All rights reserved.
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