n25q256 Numonyx, n25q256 Datasheet - Page 41

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
Table 4.
6.2.1
NVCR<4>
NVCR<3>
NVCR<2>
NVCR<1>
NVCR<0>
Bit
Non-Volatile Configuration Register
Dummy clock cycle NV configuration bits (NVCR bits from 15 to 12)
The bits from 15 to 12 of the Non Volatile Configuration register store the default settings for
the dummy clock cycles number after the fast read instructions (in all the 3 available
protocols). The dummy clock cycles number can be set from 1 up to 15 as described here,
according to operating frequency (the higher is the operating frequency, the bigger must be
the dummy clock cycle number) to optimize the fast read instructions performance.
The default values of these bits allow the memory to be safely used with fast read
instructions at the maximum frequency (108 MHz). Please note that if the dummy clock
number is not sufficient for the operating frequency, the memory reads wrong data.
Table 5.
1. All the values are guaranteed by characterization and not 100% tested in production
Dummy Clock
Reset/Hold
disable
Quad Input
Command
Dual Input
Command
128Mb selection
Address mode
selection
Parameter
10
1
2
3
4
5
6
7
8
9
Maximum operative frequency by dummy clock cycles
0
1
0
1
0
1
0
1
0
1
FASTREAD
Value
105
108
108
108
108
108
108
108
54
95
Maximum allowed frequency (MHz)
disabled
enabled (default)
enabled
disabled (default)
enabled
disabled (default)
Upper 128Mb segment
Bottom 128Mb segment
4-Byte address mode
3-Byte address mode
(default)
Description
DOFR
Micron Technology, Inc., reserves the right to change products or specifications without notice.
105
108
108
108
108
108
108
50
85
95
DIOFR
Volatile and Non Volatile Registers
105
108
108
108
108
39
59
75
88
94
Disable Pad Hold/Reset functionality
Enable command on four input line
Enable command on two input line
Define the 128Mb segment enabled
for 3-Byte operation
Define the number of address bytes
for memory instructions
(1)
©2010 Micron Technology, Inc. All rights reserved.
QOFR
105
108
108
108
108
43
56
70
83
94
Note
QIOFR
105
108
20
39
49
59
69
78
86
95
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