n25q256 Numonyx, n25q256 Datasheet - Page 124

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Instructions
9.2.15
9.2.16
124/186
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. Apart
form the parallelizing of the instruction code and the output data on the two pins DQ0 and
DQ1, the instruction functionality is exactly the same as the Read Status Register (RDSR)
instruction of the Extended SPI protocol, please refer to
Register (RDSR)
Figure 78. Read Status Register instruction sequence DIO-SPI
Write status register (WRSR)
The write status register (WRSR) instruction allows new values to be written to the status
register. Before it can be accepted, a write enable (WREN) instruction must previously have
been executed. Apart form the parallelizing of the instruction code and the input data on the
two pins DQ0 and DQ1, the instruction functionality and the protection feature management
is exactly the same as the Write Status Register (WRSR) instruction of the Extended SPI
protocol, please refer to
Figure 79. Write Status Register instruction sequence DIO-SPI
DQ0
DQ1
C
S
DQ0
DQ1
C
S
for further details.
Section 9.1.30: Write status register (WRSR)
0
Instruction
1
0
2
Instruction
1
3
7
6
2
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
5
4
3
5
Byte
Status Register Out
Status Register In
7
3
2
6
6
4
1
5
0
4
7
5
Byte
3
7
2
6
8
6
Section 9.1.29: Read Status
5
1
4
0
9 10 11
7
Byte
3
2
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1
0
for further details.
N25Q256 - 3 V