n25q256 Numonyx, n25q256 Datasheet - Page 125

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
9.2.17
9.2.18
DQ0
DQ1
DQ0
DQ1
Read Lock Register (RDLR)
The Read Lock Register instructions is used to read the lock register content.
Apart form the parallelizing of the instruction code, the address and the output data on the
two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Read Lock
Register (RDLR) instruction of the Extended SPI protocol, please refer to
Read Lock Register (RDLR)
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
Figure 80. Read Lock Register instruction and data-out sequence DIO-SPI
Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock
Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed.
Apart form the parallelizing of the instruction code, the address and the input data on the
two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Write to Lock
Register (WRLR) instruction of the Extended SPI protocol, please refer to
Write to Lock Register (WRLR)
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
Figure 81. Write to Lock Register instruction sequence DIO-SPI
C
S
C
S
Section 5.1.2: 4 Byte Address Mode on page 25
Section 5.1.2: 4 Byte Address Mode on page 25
0
0
Instruction
Instruction
1
1
2
2
3
3
23 21 19 17
23 21 19 17
22 20 18 16
22 20 18 16
4
4
for further details.
5
5
for further details.
6
6
7
7
24-Bit Address
24-bit Address
15 13 11 9
14 12 10 8
15 13 11 9
14 12 10 8
8
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
9 10 11
9 10 11
12 13 14 15
12 13 14 15
7
6
7
6
5
4
5
4
3
2
3
2
1
0
1
0
16 17 18 19
Lock Register Out
7
Lock Register In
6
12 13 14 15
7
6
5
4
©2010 Micron Technology, Inc. All rights reserved.
5
4
3
2
3
2
1
0
1
0
Section 9.1.31:
Section 9.1.32:
Instructions
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