n25q256 Numonyx, n25q256 Datasheet - Page 96

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Instructions
9.1.28
9.1.29
96/186
S
C
DQ0
DQ1
Program/Erase Resume
After a Program/Erase suspend instruction, a Program/Erase Resume instruction is
required to continue performing the suspended Program or Erase sequence.
Program/Erase Resume instruction is ignored if the device is not in a Program/Erase
Suspended status. The WIP bit of the Status Register and Program/Erase controller bit (Not
WIP) of the Flag Status Register both switch to the busy state (1 and 0 respectively) after
Program/Erase Resume instruction until the Program or Erase sequence is completed.
In this case the next Program/Erase Resume Instruction resumes the more recent
suspended modify cycles, another Program/Erase Resume Instruction is need to resume
also the former one.
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write In Progress (WIP) bit (or the Program/Erase controller bit of the Flag Status
Register) before sending a new instruction to the device. It is also possible to read the
Status Register continuously, as shown here.
Figure 45. Read Status Register instruction sequence
0
High Impedance
1
2
Instruction
3
4
5
6
7
MSB
7
8
6
9 10 11 12 13 14 15
Status Register Out
5
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
2
1
0
MSB
7
6
Status Register Out
5
4
©2010 Micron Technology, Inc. All rights reserved.
3
2
1
0
N25Q256 - 3 V
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