n25q256 Numonyx, n25q256 Datasheet - Page 46

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Volatile and Non Volatile Registers
6.4
Table 8.
6.4.1
46/186
VECR<7>
VECR<6>
VECR<5>
VECR<4>
VECR<3>
VECR<2:0>
Bit
Volatile Enhanced Configuration Register
The Volatile Enhanced Configuration Register (VECR) affects the memory configuration
after every execution of Write Volatile Enhanced Configuration Register (WRVECR)
instruction. This instruction overwrites the memory configuration set during the POR
sequence by the Non Volatile Configuration Register (NVCR). Its purpose is enabling of
QIO-SPI protocol and DIO-SPI protocol.
Volatile Enhanced Configuration Register
Quad Input Command VECR<7>
The Quad Input Command configuration bit can be used to make the memory start working
in QIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register
Quad Input
Command
Dual Input
Command
Reserved
Reset/Hold
disable
Accelerator
pin enable in
QIO-SPI
protocol or in
QIFP/QIEFP
Output Driver
Strength
HOLD (Reset) functionality disabling
To enable the VPP functionality in Quad I/O modify operations
To define output driver strength (3 bit)
Parameter
Warning:
0
1
0
1
x
0
1
0
1
000
001
010
011
100
101
110
111
WARNING: in case of both QIO-SPI and DIO-SPI enabled, the
memory works in QIO-SPI
Value
Enabled
Disabled (default)
Enabled
Disabled (default)
Reserved
Disabled
Enabled (default)
Enabled
Disabled (default)
reserved
90
60
45
reserved
20
15
30 (default)
Description
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Fixed value = 0b
Enable command on four input lines
Enable command on two input lines
Disable Pad Hold/Reset functionality
The bit must be considered in case of QIFP,
QIEFP, or QIO-SPI protocol. It is “Don’t
Care” otherwise.
Impedance at V
©2010 Micron Technology, Inc. All rights reserved.
CC
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Note
N25Q256 - 3 V