n25q256 Numonyx, n25q256 Datasheet - Page 51

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
6.5.8
that a modify operation has tried to access to a locked OTP space. The Protection Status bit
is related to all possible protection violations as follows:
Once set High, the Protection Status bit can only be reset Low (FSR<1>=0) by a Clear Flag
Status Register command (CLFSR). If set High it should be reset before a new command is
issued, otherwise the new command will appear to fail.
Protection Status bit (4-Byte)
Bit 0 of the Flag Status register represents the 4-byte address mode Status bit. It indicates
that 4-byte address mode was enabled by the Enter 4-byte Address Mode
(EN4BYTEADDR) instruction.
The bit is set (FSR<0>=1) when EN4BYTEADDR has been correctly decoded by memory.
When a Exit 4-byte address mode (EX4BYTEADDR) is issued the 4-byte address mode
Status bit returns Low (FSR<0>=0)
Clear Flag Status Register command (CLFSR) has no effect on this bit
The sector is protected by Software Protection Mode 1 (SPM1) Lock registers,
The sector is protected by Software Protection Mode 2 (SPM2) Block Protect Bits
(standard SPI Status Register),
An attempt to program OTP when locked,
A Write Status Register command (WRSR) on STD SPI Status Register when locked
by the SRWD bit in conjunction with the Write Protect (W/VPP) signal (Hardware
Protection Mode).
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Volatile and Non Volatile Registers
©2010 Micron Technology, Inc. All rights reserved.
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