n25q256 Numonyx, n25q256 Datasheet - Page 87

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
DQ0
DQ1
DQ2
DQ3
C
S
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes in the same page.
For optimized timings, it is recommended to use the Quad Input Fast Program (QIFP)
instruction to program all consecutive targeted bytes in a single sequence rather to using
several Quad Input Fast Program (QIFP) sequences each containing only a few bytes See
Table 34.: AC
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Quad Input Fast Program (QIFP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Quad Input Fast Program (QIFP) cycle is in progress,
the Status Register may be read to check the value of the Write In Progress (WIP) bit. The
Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch
(WEL) bit is reset.
A Quad Input Fast Program (QIFP) instruction applied to a page that is protected by the
Block Protect (BP3, BP2, BP1, BP0 and TB) bits is not executed.
A Quad Input Fast Program cycle can be paused by mean of Program/Erase Suspend
(PES) instruction and resumed by mean of Program/Erase Resume (PER) instruction.
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
Figure 38. Quad Input Fast Program Instruction Sequence
0
‘1’
1
Section 5.1.2: 4 Byte Address Mode on page 25
Instruction
2
3
Characteristics.
4
5
6
7
23 22 21
8
9 10
24-bit Address
Don’t Care
Don’t Care
Don’t Care
3
28 29 30 31 32 33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
1
0
4
7
MSB
5
6
1
Data In
3
0
1
2
34 35 36
4
7
MSB
5
6
2
0
1
3
2
7
MSB
4
5
6
©2010 Micron Technology, Inc. All rights reserved.
3
Data In
37
0
1
3
2
MSB
38
4
5
7
6
4
39
3
0
1
2
40
4
5
7
6
MSB
5
Data In
41
0
1
2
3
Instructions
42
4
5
7
6
MSB
6
43
1
2
3
0
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