n25q256 Numonyx, n25q256 Datasheet - Page 89

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
S
C
DQ0
S
C
DQ0
Bit 0 of the OTP control byte, that is byte 64, is used to permanently lock the OTP memory
array.
Once a bit of the OTP memory has been programmed to '0', it can no longer be set to '1'.
Therefore, as soon as bit 0 of byte 64 (control byte) is set to '0', the 64 bytes of the OTP
memory array become read-only in a permanent way.
Any Program OTP (POTP) instruction issued while an Erase, Program or Write cycle is in
progress is rejected without having any effect on the cycle that is in progress.
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
Figure 40. Program OTP instruction sequence
MSB
7
40
0
6
When bit 0 of byte 64 = '1', the 64 bytes of the OTP memory array can be programmed.
When bit 0 of byte 64 = '0', the 64 bytes of the OTP memory array are read-only and
cannot be programmed anymore.
41
1
5
42
Data byte 2
Section 5.1.2: 4 Byte Address Mode on page 25
2
Instruction
4
43 44 45 46 47 48 49 50
3
3
4
2
5
1
6
0
MSB
7
7
MSB
23
8
6
22 21
9 10
5
Data byte 3
24-bit address
4
51
3
52 53 54 55
3
28 29 30 31 32 33 34 35
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
1
1
0
0
MSB
7
MSB
7
6
6
5
Data byte 1
5
Data byte n
4
4
3
36 37 38
3
©2010 Micron Technology, Inc. All rights reserved.
2
2
1
1
0
39
0
Instructions
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