n25q256 Numonyx, n25q256 Datasheet - Page 165

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
10.2
Note:
Enter XIP mode by setting the Volatile Configuration Register
To use the Volatile Configuration Register method to enter XIP mode, it is necessary to write
a 0 to bit 3 of the Volatile Configuration Register to make the device ready to enter XIP
mode (2). This instruction doesn't permit to enter XIP state directly: a Fast Read instruction
(either Single, Dual or Quad) is needed once to start the XIP Reading.
After the Fast Read instruction (Single, Dual or Quad) the XIP confirmation bit must be set
to 0. (first bit on DQ0 during the first dummy cycle after the address has been received),
Then after the next de-select and select cycle (S pin set to 1 and then to 0) the memory
codify the first 3 bytes received on the input pin(s) directly as an address, without any
instruction code, and after the dummy clock cycles (configurable) directly outputs the data.
For example to enable the XIP (without enter) with six dummy clock cycles, the pattern in
Table 27.: VCR XIP bits setting example
for example, in XIP mode from extended SPI read mode by mean of Quad Input Output Fast
Read instruction, as described in
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
For devices with a feature set digit equal to 2 or 4 in the part number (Basic XiP), it is not
necessary to set the Volatile Configuration Register bit 3 to enter in XIP mode: it is possible
to enter directly in XIP mode by setting XIP Confirmation bit to 0 during the first dummy
clock cycle after a fast read instruction. See
Table 27.
81h (WRVCR opcode)
Section 5.1.2: 4 Byte Address Mode on page 25
VCR XIP bits setting example
Table 27.: VCR XIP bits setting
6 dummy
+ 0110
cycles
Micron Technology, Inc., reserves the right to change products or specifications without notice.
must be issued, and after that it is possible to enter,
Section 16: Ordering
Ready for
XIP
0
Reserved
©2010 Micron Technology, Inc. All rights reserved.
example.
0
information.
XIP Operations
Configuration
Wrap Mode
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