n25q256 Numonyx, n25q256 Datasheet - Page 70

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Instructions
9.1.6
Note:
70/186
DQ0
DQ1
S
C
Read Serial Flash Discovery Parameter
The Read Serial Flash Discovery Parameter (RDSFDP) instruction allows reading the Serial
Flash Discovery Parameter area (SFDP).
This SFDP area is composed of 2048 read-only bytes containing operating characteristics
and vendor specific information. The SFDP area is factory programmed.
Data to be written to the SFDP area is in definition phase.
If the SFDP area is blank, the device is shipped with all the SFDP bytes at FFh. If only a
portion of the SFDP area is written to, the portion not used is shipped with bytes in erased
state (FFh).
The instruction sequence for RDSFDP has the same structure as that of a Fast Read
instruction. First, the device is selected by driving Chip Select (S) Low. Next, the 8-bit
instruction code (5Ah) and the 24-bit address are shifted in, followed by 8 dummy clock
cycles.
The bytes of SFDP content are shifted out on the Serial Data Output (DQ1) starting from the
specified address. Each bit is shifted out during the falling edge of Serial Clock (C). The
Read SFDP instruction is terminated by driving Chip Select (S) High at any time during data
output. SFDP area is always addressable by means 3 byte regardless active address mode
Figure 23. Read Serial Flash Discovery Instruction and Data-out Sequence
DQ0
DQ1
S
C
7
0
32 33 34
1
6
High Impedance
Dummy cycles
2
5
Instruction
4
3
35
3
4
36 37 38 39 40 41 42 43 44 45 46
5
2
6
1
0
7
MSB
23
7
8
22 21
9 10
6
24-bit address
5
DATA OUT 1
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
28 29 30 31
3
2
2
1
1
0
0
47
MSB
7
6
5
DATA OUT 2
4
©2010 Micron Technology, Inc. All rights reserved.
3
2
1
0
MSB
7
N25Q256 - 3 V