n25q256 Numonyx, n25q256 Datasheet - Page 146

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Instructions
9.3.9
146/186
Program OTP instruction (POTP)
The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP
memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable
(WREN) instruction must have been executed.
Apart form the parallelizing of the instruction code, address and input data on the four pins
DQ0, DQ1, DQ2 and DQ3, the instruction functionality (as well as the locking OTP method)
is exactly the same as the Program OTP (POTP) instruction of the Extended SPI protocol,
please refer to
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
Figure 109. Program OTP instruction sequence QIO-SPI
S
DQ0
DQ2
C
DQ1
DQ3
Section 5.1.2: 4 Byte Address Mode on page 25
Section 9.1.23: Program OTP instruction (POTP)
Instruction
0
1
20 16 12 8
21 17 13 9
22 18 14 10
23 19 15 11 7
2
24-Bit Address
3
4
5
6
5
6
4
2
7
1
0
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
8
6
byte1
4
5
7
Data
9 10 11 12 13 14
2
0
1
3
5
6
4
7
byte 2
Data
1
2
0
3
byte n
5
6
4
7
Data
1
2
3
0
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N25Q256 - 3 V