n25q256 Numonyx, n25q256 Datasheet - Page 66

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Instructions
9.1.2
66/186
DQ0
DQ1
S
C
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data output (DQ1), each bit being shifted out, at a
maximum frequency fR, during the falling edge of Serial Clock (C).
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 00000000h, allowing the read
sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
Figure 19. Read Data Bytes instruction and data-out sequence
0
1
High Impedance
Section 5.1.2: 4 Byte Address Mode on page 25
2
Instruction
3
4
5
6
7
MSB
23
8
22 21
9 10
24-bit address
3
28 29 30 31 32 33 34 35
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
1
0
MSB
7
6
5
Data Out 1
4
3
36 37 38
©2010 Micron Technology, Inc. All rights reserved.
2
1
0
39
7
Data Out 2
N25Q256 - 3 V