n25q256 Numonyx, n25q256 Datasheet - Page 80

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Instructions
9.1.15
80/186
DQ0
DQ1
DQ0
DQ1
Read OTP (ROTP)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a dummy byte. Each
bit is latched in on the rising edge of Serial Clock (C).
Then the memory contents at that address are shifted out on Serial Data output (DQ1).
Each bit is shifted out at the maximum frequency, fCmax, on the falling edge of Serial Clock
(C). The instruction sequence is shown in Figure 17.
The address is automatically incremented to the next higher address after each byte of data
is shifted out.
There is no rollover mechanism with the Read OTP (ROTP) instruction. This means that the
Read OTP (ROTP) instruction must be sent with a maximum of 65 bytes to read. All other
bytes outside the OTP area are “Don’t Care.”
The Read OTP (ROTP) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read OTP (ROTP)
instruction issued while an Erase, Program or Write cycle is in progress, is rejected without
having any effect on the cycle that is in progress.
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
Figure 32. Read OTP instruction and data-out sequence
C
S
S
C
7
32 33 34
Section 5.1.2: 4 Byte Address Mode on page 25
0
6
1
High Impedance
Dummy cycles
5
2
Instruction
4
35
3
3
36 37 38 39 40 41 42 43 44 45 46
4
2
5
1
6
0
7
MSB
7
23
8
6
22 21
9 10
5
DATA OUT 1
24-bit address
4
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
28 29 30 31
2
2
1
1
0
47
0
MSB
7
6
5
DATA OUT n
4
3
©2010 Micron Technology, Inc. All rights reserved.
2
1
0
MSB
7
N25Q256 - 3 V