n25q256 Numonyx, n25q256 Datasheet - Page 115

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
9.2.3
DQ0
DQ1
C
S
0
Instruction
1
Dual Command Fast Read (DCFR)
The Dual Command Fast Read (DCFR) instruction allows to read the memory in DIO-SPI
protocol, parallelizing the instruction code, the address and the output data on two pins
(DQ0 and DQ1). The Dual Command Fast Read (DCFR) instruction can be issued, when
the device is set in DIO-SPI mode, by sending to the memory indifferently one of the 3
instructions codes: 0Bh, 3Bh or BBh, the effect is exactly the same. The 3 instruction codes
are all accepted to help the application code porting from Extended SPI protocol to DIO-SPI
protocol.
Apart for the parallelizing on two pins of the instruction code, the Dual Command Fast Read
instruction functionality is exactly the same as the Dual I/O Fast Read of the Extended SPI
protocol, please refer to
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
Figure 64. Dual Command Fast Read instruction and data-out sequence DIO-SPI
2
3
23 21 19 17
22 20 18 16
4
Section 5.1.2: 4 Byte Address Mode on page 25
5
6
7
24-bit Address
15 13 11 9
14 12 10 8
8
9 10 11
Section 9.1.9: Dual I/O Fast Read
12 13 14 15
7
6
5
4
3
2
1
0
16 17 18 19 20 21 22 23 24 25 26 27 28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Dummy cycles
for further details.
7
MSB
6
Data Out 1
©2010 Micron Technology, Inc. All rights reserved.
5
4
3
2
1
0
MSB
6
7
Data Out n
4
5
Instructions
2
3
0
1
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