n25q256 Numonyx, n25q256 Datasheet - Page 108

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Instructions
9.1.43
9.1.44
9.1.45
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Enter 4-Byte Address Mode
The Enter 4-byte address mode (EN4BYTEADDR) instruction enables 4-byte address
mode.
Before it can be accepted, a write enable (WREN) instruction must previously have been
executed. After the write enable (WREN) instruction has been decoded and executed, the
device sets the write enable latch (WEL).
Figure 59. Enter 4-Byte Address Mode Instruction Sequence
Exit 4-Byte Address Mode
The Exit 4-byte address mode (EX4BYTEADDR) instruction disables 4-byte address mode.
Before it can be accepted, a write enable (WREN) instruction must previously have been
executed. After the write enable (WREN) instruction has been decoded and executed, the
device sets the write enable latch (WEL).
Figure 60. Exit 4-Byte Address Mode Instruction Sequence
Reset Enable
The Reset operation is used as a system software reset that puts the device in the power-on
reset condition. All the lock bits, volatile configuration registers, and the extended address
register are reset to the power-on reset default condition after the reset software sequence
has been accepted. The power-on reset condition depends on non volatile configuration
register content. This Reset operation consists of two instructions: Reset Enable and Reset
Memory.
The Reset operation requires the Reset Enable instruction followed by the Reset Memory
instruction. If the Reset Enable instruction is followed by any instruction other than Reset
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N25Q256 - 3 V