n25q256 Numonyx, n25q256 Datasheet - Page 67

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
9.1.3
DQ0
DQ1
S
C
Read Data Bytes using 4 Byte Address (READ4BYTE)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes using 4 Bytes Address (READ4BYTE) instruction is followed by a 4-byte
address (A31-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then
the memory contents, at that address, is shifted out on Serial Data output (DQ1), each bit
being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (C).
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single instruction. When the highest address is reached, the
address counter rolls over to 00000000h, allowing the read sequence to be continued
indefinitely.
This instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven
High at any time during data output. Any instruction, while an Erase, Program, or Write cycle
is in progress, is rejected without having any effects on the cycle that is in progress.
EAR becomes 'don't care' while the instruction code is executed, and neither FSR<0> not
NVCR<0> are modified by this command, so the addressing mode returns in the formerly
selected mode after the operation is completed.
Figure 20. Read Data Bytes using 4 Byte Address Instruction and Data-Out
0
1
High Impedance
2
Sequence
Instruction
3
4
5
6
7
MSB
31
8
30 29
9 10
32-bit address
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
36 37 38 39 40 41 42 43
2
1
0
MSB
7
6
5
Data Out 1
4
©2010 Micron Technology, Inc. All rights reserved.
3
44 45 46
2
1
0
47
7
Data Out 2
Instructions
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