n25q256 Numonyx, n25q256 Datasheet - Page 163

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
10.1
Yes
XiP Confirmation
Is XIP enabled ?
NVCR Check
Power On
XIP mode
bit = 0 ?
Figure 132. Read functionality Flow Chart
Enter XIP mode by setting the Non Volatile Configuration
Register
To use the Non Volatile Configuration Register method to enter in XIP mode it is necessary
to set the Non Volatile Configuration Register bits from 11 to 9 with the pattern
corresponding to the required XIP mode by mean of the Write Non Volatile Configuration
Register (WRNVCR) instruction. (See
This instruction doesn't affect the XIP state until the next Power on sequence. In this case,
after the next power on sequence, the memory directly accept addresses and then, after the
dummy clock cycles (configurable), outputs the data as described in
bits setting
dummy clock cycles the following pattern must be issued:
Yes
No
example. For example to enable XIP on QIOFR in normal SPI protocol with six
No
SPI standard mode (no
XiP, VCR <3> = 1)
Table 26.: NVCR XIP bits setting
Micron Technology, Inc., reserves the right to change products or specifications without notice.
VCR<3> = 0 ?
No
Yes
No
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SPI mode (no XIP) but
Read Instructions ?
Table 26.: NVCR XIP
ready to enter XIP
XiP Confirmation
example.)
bit = 0 ?
XIP Operations
Yes
Yes
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No