n25q256 Numonyx, n25q256 Datasheet - Page 120

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Instructions
9.2.9
120/186
DQ0
DQ1
DQ0
DQ1
C
S
C
S
Figure 71. Dual Command Page Program instruction sequence DSP, D2h
Program OTP instruction (POTP)
The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP
memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed.
Apart form parallelizing the instruction code, address, and input data on pins DQ0 and DQ1,
the instruction functionality and the locking OTP method are the same as the Program OTP
(POTP) instruction of the Extended SPI protocol; refer to
instruction (POTP)
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
Figure 72. Program OTP instruction sequence DIO-SPI
0
0
Instruction
Instruction
1
1
2
Section 5.1.2: 4 Byte Address Mode on page 25
2
3
3
23 21 19 17
22 20 18 16
23 21 19 17
22 20 18 16
4
4
5
5
for further details.
6
6
7
7
24-bit Address
15 13 11 9
14 12 10 8
24-Bit Address
8
15 13 11 9
14 12 10 8
8
9 10 11
9 10 11
12 13 14 15
7
6
12 13 14 15
7
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
5
4
5
4
3
2
3
2
1
0
1
0
16 17 18 19
7
6
Data Byte 1
16 17 18 19
7
6
Data Byte 1
5
4
5
4
3
2
Section 9.1.23: Program OTP
3
2
1
0
1
0
20 21 22 23
7
6
Data Byte 2
20 21 22 23 24 25 26 27
©2010 Micron Technology, Inc. All rights reserved.
7
6
5
Data Byte 2
4
5
4
3
2
3
2
1
0
1
0
Dual_Program_OTP
1036
7
6
6
7
N25Q256 - 3 V
Data Byte 256
Data Byte n
1037
5
4
4
5
1038
3
2
2
3
1039
1
0
1
0