n25q256 Numonyx, n25q256 Datasheet - Page 167

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
10.4
XIP Memory reset after a controller reset
If during the application life the system controller is reset during operation, and the device
features the RESET functionality (in devices with a dedicated part number), and the feature
has not been disabled, after the controller resets, the memory returns to POR state and
there is no issue. See
In all the other cases, it is possible to exit the memory from the XIP mode by sending the
following rescue sequence at the first chip selection after a system reset:
DQ0 (PAD DATA) equal to '1' for:DQ0= '1' for:
7 clock cycles within S low (S becomes high before 8th clock cycle)
+ 9 clock cycles within S low (S becomes high before 10th clock cycle)
+ 13 clock cycles within S low (S becomes high before 14th clock cycle)
+ 17 clock cycles within S low (S becomes high before 18th clock cycle)
+ 25 clock cycles within S low (S becomes high before 26th clock cycle)
+ 33 clock cycles within S low (S becomes high before 34th clock cycle)
The global effect is only to exit from XIP without any other reset.
Power-on Reset state means that all the lock bits, volatile configuration registers, and the
extended address register have been reset in the power-on reset default condition. The
power-on reset condition depends on non volatile configuration register content.
Section 16: Ordering
Micron Technology, Inc., reserves the right to change products or specifications without notice.
information.
©2010 Micron Technology, Inc. All rights reserved.
XIP Operations
167/186