n25q256 Numonyx, n25q256 Datasheet - Page 98

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Instructions
Table 21.
1. As defined by the values in the Block Protect (TB, BP3, BP2, BP1, BP0) bits of the Status Register, as shown in
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1
0
1
0
W / VPP
Signal
Status register
0
0
1
1
SRWD
bit
When the Status Register Write Disable (SRWD) bit of the Status Register is set to '1', two
cases need to be considered, depending on the state of Write Protect (W/VPP):
Regardless of the order of the two events, the Hardware Protected mode (HPM) can be
entered in either of the following ways:
The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write
Protect (W/VPP) High.
If Write Protect (W/VPP) is permanently tied High, the Hardware Protected mode (HPM) can
never be activated, and only the Software Protected mode (SPM), using the Block Protect
(BP3, BP2, BP1, BP0) bits of the Status Register, can be used.
Protection modes
format.
If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction.
If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register
even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction (attempts to write to the Status Register are rejected, and are not
accepted for execution). As a consequence, all the data bytes in the memory area that
are software protected (SPM) by the Block Protect (BP3, BP2, BP1, BP0) bits of the
Status Register, are also hardware protected against data modification.
setting the Status Register Write Disable (SRWD) bit after driving Write Protect
(W/VPP) Low
driving Write Protect (W/VPP) Low after setting the Status Register Write Disable
(SRWD) bit.
Software
protected
(SPM)
Hardware
protected
(HPM)
Mode
Status register is writeable, if the
WREN instruction has set the WEL
bit.
The values in the SRWD, TB, BP3,
BP2, BP1, and BP0 bits can be
changed.
Status Register is hardware write
protected. The values in the
SRWD, TB, BP3, BP2, BP1 and
BP0 bits cannot be changed
Write protection of the status
register
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Protected against PP,
DIFP, DIEFP, QIFP,
QIEFP, SSE, SE and
BE instructions.
PP, DIFP, DIEFP,
QIFP, QIEFP, SSE,
SE and BE
instructions.
Protected area
Memory content
©2010 Micron Technology, Inc. All rights reserved.
(1)
Ready to accept PP,
DIFP, DIEFP, QIFP,
QIEFP, SSE, and SE
instructions.
PP, DIFP, DIEFP,
QIFP, QIEFP, SSE,
and SE instructions.
Unprotected area
N25Q256 - 3 V
Table 3:
(1)