n25q256 Numonyx, n25q256 Datasheet - Page 151

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
9.3.17
9.3.18
Read Lock Register (RDLR)
The Read Lock Register instructions is used to read the lock register content. Apart from
parallelizing the instruction code, the address, and the output data on four pins (DQ0, DQ1,
DQ2, DQ3) the instruction functionality is the same as the Read Lock Register (RDLR)
instruction of the Extended SPI protocol. Refer to
(RDLR)
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
Figure 117. Read Lock Register instruction and data-out sequence QIO-SPI
Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock
Registers. Before it can be accepted, a Write Enable (WREN) instruction must have been
executed. Apart form the parallelizing of the instruction code, the address, and the input
data on the four pins DQ0, DQ1, DQ2 DQ3, the instruction functionality is exactly the same
as the Write to Lock Register (WRLR) instruction of the Extended SPI protocol. Please refer
to
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
Figure 118. Write to Lock Register instruction sequence QIO-SPI
Section 9.1.32: Write to Lock Register (WRLR)
for further details.
DQ0
Section 5.1.2: 4 Byte Address Mode on page 25
DQ3
Section 5.1.2: 4 Byte Address Mode on page 25
DQ1
DQ2
S
C
DQ0
DQ2
DQ3
DQ1
S
C
Instruction
0
Instruction
1
0
21 17 13 9
20 16 12 8
2
22 18 14 10 6
23 19 15 11 7
1
3
24-bit Address
2
21 17 13 9
20 16 12 8
22 18 14 10
23 19 15 11 7
4
24-bit Address
3
5
4
6
5
4
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
7
1
0
2
3
6
8
5
6
4
6
7
4
5
7
9 10 11 12 13 14 15
1
0
3
2
2
0
1
3
Lock Register Out
8
5
4
7
6
6
4
5
Lock Register In
7
9
Section 9.1.31: Read Lock Register
1
0
3
for further details.
2
2
0
1
3
4
5
7
6
0
1
3
2
4
5
7
6
0
1
3
2
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Instructions
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