n25q256 Numonyx, n25q256 Datasheet - Page 147

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
9.3.10
9.3.11
Subsector Erase (SSE)
The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector.
Before it can be accepted, a Write Enable (WREN) instruction must have been executed.
Apart form the parallelizing of the instruction code and the address on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Subsector Erase
(SSE) instruction of the Extended SPI protocol, please refer to
Erase (SSE)
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
Figure 110. Subsector Erase instruction sequence QIO-SPI
Sector Erase (SE)
The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must have been executed.
Apart form the parallelizing of the instruction code and the address on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Sector Erase
(SE) instruction of the Extended SPI protocol, please refer to
(SE)
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
Figure 111. Sector Erase instruction sequence QIO-SPI
for further details.
Section 5.1.2: 4 Byte Address Mode on page 25
Section 5.1.2: 4 Byte Address Mode on page 25
for further details.
DQ0
DQ2
DQ1
DQ3
S
C
DQ0
DQ2
DQ3
DQ1
C
S
Instruction
0
Instruction
1
0
2
21 17 13 9
20 16 12 8
22 18 14 10
1
23 19 15 11 7
24-Bit Address
3
2
21 17 13 9
20 16 12 8
22 18 14 10
23 19 15 11 7
24-bit Address
4
3
5
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
6
5
6
4
5
7
2
1
0
3
6
6
4
5
8
7
2
1
0
3
9
8
9
Section 9.1.25: Sector Erase
Section 9.1.24: Subsector
©2010 Micron Technology, Inc. All rights reserved.
Instructions
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