n25q256 Numonyx, n25q256 Datasheet - Page 109

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
S#
C
DQ0
Memory, it is disabled. Reset Memory is also disabled if the device is selected by driving
chip select (S) and Clock (C) low.
The Reset Enable instruction is entered by driving S low, followed by the instruction code on
serial data input (DQ0). The Reset Memory instruction is entered by driving S low, followed
by the instruction code on DQ0.
Minimum deselection time between the Reset Enable instruction and the Reset Memory
instruction must be set according to the tSHSL2 specification; otherwise, reset software is
not guaranteed.
If a Reset operation is begun while an internal Write, Program, or Erase operation is in
progress or suspended, the internal operation is affected and data might be lost. As soon as
S is driven high after the Reset Memory instruction is issued, the device enters the Reset
mode and a time of tSHSL3 is then required before the device can be reselected by driving
S low. You should exit XiP mode before entering software reset as described in
mode hold and
Figure 61. Reset Enable and Reset Memory Instruction Sequence
0
1
2
exit.
Reset Enable
3
4
5
6
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0
1
2
Reset Memory
3
©2010 Micron Technology, Inc. All rights reserved.
4
5
6
7
Instructions
10.3: XIP
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