n25q256 Numonyx, n25q256 Datasheet - Page 164

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

XIP Operations
Table 26.
164/186
(WRNVCR
opcode)
B1h
DQ0
DQ3
DQ1
DQ2
Xb is the XIP Confirmation bit and should be set as follows: 0 to keep XIP state; 1 to exit XIP mode and return to standard read mode.
Vd
S
NVCR check: XIP enabled
cycles for fast
NVCR XIP bits setting example
Figure 133. XIP mode directly after power on
instructions
t
6 dummy
VSI
+ 0110
(<100μ)
read
C
default; Quad
Mode 3
Mode 0
XIP set as
I/O mode
100
0
22 18 14 10
23 19 15 11
20 16 12 8
21 17 13 9
24-bit Address
1
driver strength
Output Buffer
2
default
3
111
4
4
5
6
7
5
0
1
2
3
6
Xb
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Dummy Cycles
7
Don’t Care
8
9 10 11 12 13 14
x
Byte 1
6
7
4
5
IO switches from Input to Output
not disabled
Hold/Reset
1
2
3
0
Byte 2
6
7
4
5
1
15 16
3
1
2
0
©2010 Micron Technology, Inc. All rights reserved.
6
7
4
5
SPI protocol
Extended
11
N25Q256 - 3 V
(Default)
Address
Activate
4-byte
11