n25q256 Numonyx, n25q256 Datasheet - Page 139

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
9.3.4
DQ0
DQ3
DQ1
DQ2
C
S
Mode 3
Mode 0
Figure 99. Quad Command Fast Read instruction and data-out sequence QSP, EBh
Quad Command Fast Read using 4 Byte Address (QCFR4Byte)
The Quad Command Fast Read using 4 byte address (QCFR4BYTE) instruction allows to
read the memory in QIO-SPI protocol, parallelizing the instruction code, the address and the
output data on four pins (DQ0, DQ1, DQ2 and DQ3). The instruction can be issued, after the
device is set in QIO-SPI mode, by sending to the memory indifferently one of the 3
instructions codes: 0Ch, 6Ch or ECh, the effect is exactly the same. The 3 instruction codes
are all accepted to help the application code porting from Extended SPI protocol to QIO-SPI
protocol.
Apart for the parallelizing on four pins of the instruction code, the Quad Command Fast
Read using 4 byte address instruction functionality is exactly the same as the Quad I/O
Fast Read of the Extended SPI protocol.
Instruction
0
1
21 17 13 9
20 16 12 8
22 18 14 10 6
23 19 15 11 7
2
24-bit Address
3
4
5
5
4
6
1
0
2
3
7
8
9 10
Dummy Cycles
Micron Technology, Inc., reserves the right to change products or specifications without notice.
15 16 17 18
Byte 1 Byte 2
IO switches from Input to Output
5
4
6
7
1
19
0
3
2
20
4
5
7
6
1
21
0
3
2
22
4
Byte 3 Byte 4
5
7
6
23
0
1
3
2
©2010 Micron Technology, Inc. All rights reserved.
24
4
5
7
6
25 26 27
0
1
3
2
4
4
4
Byte 5 Byte 6
4
0
0
0
0
4
4
4
4
Instructions
0
0
0
0
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