n25q256 Numonyx, n25q256 Datasheet - Page 150

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Instructions
9.3.15
9.3.16
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Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. Apart
form the parallelizing of the instruction code and the output data on the four pins DQ0, DQ1,
DQ2 and DQ3, the instruction functionality is exactly the same as the Read Status Register
(RDSR) instruction of the Extended SPI protocol, please refer to
Status Register (RDSR)
Figure 115. Read Status Register instruction sequence QIO-SPI
Write status register (WRSR)
The write status register (WRSR) instruction allows new values to be written to the status
register. Before it can be accepted, a write enable (WREN) instruction must have been
executed. The instruction code and input data are sent on four pins DQ0, DQ1, DQ2 DQ3.
The instruction functionality is exactly the same as the Write Status Register (WRSR)
instruction of the Extended SPI protocol (See
However, the protection feature management is different. In particular, once SRWD bit is set
to '1' the device enters in the hardware protected mode (HPM) independently from Write
Protect (W/VPP) signal value. To exit the HPM mode is needed to switch temporarily to the
Extended SPI protocol.
Figure 116. Write Status Register instruction sequence QIO-SPI
DQ0
DQ1
DQ3
DQ2
S
C
Instruction
0
DQ0
DQ1
DQ3
DQ2
1
S
C
for further details.
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Status Register Out
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
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Status Register In
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Section 9.1.30: Write status register
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©2010 Micron Technology, Inc. All rights reserved.
0
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Section 9.1.29: Read
N25Q256 - 3 V
(WRSR)).