n25q256 Numonyx, n25q256 Datasheet - Page 141

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
9.3.5
Note:
DQ0
DQ1
DQ3
DQ2
C
S
Figure 102. Quad Command Fast Read using 4 Byte Address Instruction QSP, ECh
Read OTP (ROTP)
The Read OTP (ROTP) instruction is used to read the 64 bytes OTP area in the QIO-SPI
protocol. The instruction functionality is exactly the same as the Read OTP instruction of the
Extended SPI protocol. The only difference is that in the QIO-SPI protocol instruction code,
address and output data are all parallelized on the four pins DQ0, DQ1, DQ2 and DQ3.
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
The dummy byte bits can not be parallelized: 8 clock cycles are requested to perform the
internal reading operation.
0
1
Section 5.1.2: 4 Byte Address Mode on page 25
A31-24 A23-16 A15-8
29 25 21 17
28 24 20 16
30 26 22 18
31 27 23 19
2
3
4
Address
5
13 9
12 8
14 10
15 11
6
7
A7-0
5
4
6
7
8
1
0
9 10
2
3
Dummy Cycles
Micron Technology, Inc., reserves the right to change products or specifications without notice.
17 18 19 20
Byte 1 Byte 2
IO switches from Input to Output
5
4
6
7
1
21
0
3
2
22
5
4
7
6
23
0
1
3
2
24
Byte 3 Byte 4
4
5
7
6
©2010 Micron Technology, Inc. All rights reserved.
25
0
1
3
2
26
4
5
7
6
27 28 29
0
1
3
2
4
4
4
Byte 5 Byte 6
4
0
0
0
0
Instructions
4
4
4
4
0
0
0
0
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