n25q256 Numonyx, n25q256 Datasheet - Page 142

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Instructions
9.3.6
9.3.7
142/186
DQ0
DQ1
DQ3
DQ2
Figure 103. Read OTP instruction and data-out sequence QIO-SPI
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. Apart form the
parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the
instruction functionality is exactly the same as the Write Enable instruction of the Extended
SPI protocol, please refer to
Figure 104. Write Enable instruction sequence QIO-SPI
Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit.
Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and
DQ3, the instruction functionality is exactly the same as the Write Disable (WRDI)
instruction of the Extended SPI protocol, please refer to
(WRDI)
C
S
for further details.
Instruction
0
1
21 17 13 9
20 16 12 8
22 18 14 10
23 19 15 11
2
DQ0
DQ3
DQ1
DQ2
S
C
3
4
Section 9.1.16: Write Enable (WREN)
5
5
4
6
7
6
Instruction
0
1
0
2
3
7
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
8
9 10
Dummy (ex.: 10)
15 16 17 18
Section 9.1.17: Write Disable
5
4
6
7
out 1
Data
1
19
0
3
2
©2010 Micron Technology, Inc. All rights reserved.
20
5
4
7
out n
6
Data
for further details.
21
1
0
3
2
22
4
5
7
6
23
0
1
3
2
N25Q256 - 3 V