n25q256 Numonyx, n25q256 Datasheet - Page 161

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
9.3.31
Reset Enable and Reset Memory, Quad I/O
The Reset Enable and Reset Memory operation is used as a system software reset that
puts the device in the power-on reset condition.
This operation consists of two instructions: Reset Enable and Reset Memory.
The Reset operation requires the Reset Enable instruction followed by the Reset Memory
instruction. If the Reset Enable instruction is followed by any instruction other than Reset
Memory, it is disabled. Reset Memory is also disabled if the device is selected by driving
chip select (S) and Clock (C) low.
This instruction functions exactly as the Reset Enable instruction of the Extended SPI
protocol, except that for this instruction the instruction code and input data are on four pins,
DQ0, DQ1, DQ2 and DQ3.
Figure 131. Reset Enable and Reset Memory Instruction Sequence, Quad I/O
DQ0
DQ1
DQ2
DQ3
S#
C
0
1
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1
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