n25q256 Numonyx, n25q256 Datasheet - Page 131

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q256 - 3 V
9.2.29
9.2.30
Enter 4-Byte Address Mode, Dual I/O
The Enter 4-Byte Address Mode instruction enables 4-byte address mode. Before this
command can be accepted, a Write Enable instruction must have been executed previously.
After the Write Enable instruction has been decoded and executed, the device sets the write
enable latch (WEL) bit.
This instruction functions exactly as the Enter 4-Byte Address Mode instruction of the
Extended SPI protocol, except that for this instruction the instruction code and input data are
on two pins, DQ0 and DQ1.
Figure 92. Enter 4-Byte Address Mode Instruction Sequence, Dual I/O
Exit 4-Byte Address Mode, Dual I/O
The Exit 4-Byte Address Mode instruction disables 4-byte address mode. Before this
instruction can be accepted, a Write Enable instruction must have been executed
previously. After the Write Enable instruction has been decoded and executed, the device
sets the write enable latch (WEL) bit.
This instruction functions exactly as the Exit 4-Byte Address Mode instruction of the
extended SPI protocol, except that for this instruction the instruction code and input data are
on two pins, DQ0 and DQ1.
Figure 93. Exit 4-Byte Address Mode Instruction Sequence, Dual I/O
DQ0
DQ1
DQ0
DQ1
S#
C
S#
C
0
0
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