n25q256 Numonyx, n25q256 Datasheet - Page 88

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Instructions
9.1.22
9.1.23
88/186
DQ0
DQ1
DQ3
DQ2
C
S
Quad Input Extended Fast Program
The Quad Input Extended Fast Program (QIEFP) instruction is very similar to the Quad
Input Extended Fast Program (QIFP), except that the address bits are shifted in on four pins
(pin DQ0, pin DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3) instead of only one.
If 4-byte address mode is enabled, the device uses a 32-bit address as explained and
shown in
Figure 39. Quad Input Extended Fast Program instruction sequence
Program OTP instruction (POTP)
The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP
memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN)
instruction has been decoded, the device sets the Write Enable Latch (WEL) bit.
The Program OTP instruction is entered by driving Chip Select (S) Low, followed by the
instruction opcode, three address bytes and at least one data byte on Serial Data input
(DQ0). Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Program OTP instruction is not executed.
There is no rollover mechanism with the Program OTP (POTP) instruction. This means that
the Program OTP (POTP) instruction must be sent with a maximum of 65 bytes to program,
once all 65 bytes have been latched in, any following byte will be discarded.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Program OTP cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Program OTP cycle, and it is 0 when it is completed. At
some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is
reset. To lock the OTP memory:
0
‘1’
Don’t Care
Don’t Care
1
Section 5.1.2: 4 Byte Address Mode on page 25
Instruction
2
3
4
5
6
7
23 19 15
20 16 12 8
21 17 13 9
22 18 14 10
8
24-bit Address
9 10
11
11 12 13 14 15 16
7
5
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
4
3
1
2
0
5
6
7
4
MSB
1
Data In
2
3
1
0
7
5
6
4
MSB
2
3
17 18 19
1
2
0
7
5
6
4
MSB
3
Data In
1
2
3
0
20
6
7
5
MSB
4
©2010 Micron Technology, Inc. All rights reserved.
4
3
21
1
2
0
22
7
5
6
4
MSB
5
Data In
23
3
1
2
0
24
5
6
7
4
MSB
6
N25Q256 - 3 V
25
2
3
1
0
7
26
5
6
4
MSB
7
27
3
1
2
0