n25q256 Numonyx, n25q256 Datasheet - Page 168

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Power-up and power-down
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Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on VCC) until VCC reaches the correct value:
A safe configuration is provided in
To avoid data corruption and inadvertent write operations during power-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less
than the Power On Reset (POR) threshold voltage, VWI - all operations are disabled, and
the device does not respond to any instruction.
During a standard power-up phase the device ignores all the instructions but RDSR and
RFSR (they can be used to check the memory internal state according to
Power-up
After power-up, the device is in the following state:
Normal precautions must be taken for supply line decoupling, to stabilize the VCC supply.
Each device in a system should have the VCC line decoupled by a suitable capacitor close
to the package pins (generally, this capacitor is of the order of 100 nF).
At power-down, when VCC drops from the operating voltage, to below the Power On Reset
(POR) threshold voltage, VWI, all operations are disabled and the device does not respond
to any instruction (the designer needs to be aware that if power-down occurs while a Write,
Program or Erase cycle is in progress, some data corruption may result).
VPPH must be applied only when VCC is stable and in the VCC(min) to VCC(max) voltage
range.
Figure 135. Power-up timing
V
V
C C
C C
VCC(min) at power-up
VSS at power-down
The device is in the Standby Power mode
The Write Enable Latch (WEL) bit is reset
The Write In Progress (WIP) bit is reset
The Lock Registers are configured as: (Write Lock bit, Lock Down bit) = (0,0).
(m a x )
(m in )
V
V c c
W I
timing.
C h ip
re s e t
C h ip s e le c tio n n o t a llo w e d
Section 3: SPI
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
V T W
P o l l i n g a l l o w e d
S P I p ro to c o l
W IP = 1
W E L = 0
= t
Modes.
V T R
©2010 Micron Technology, Inc. All rights reserved.
S ta rti n g p ro to c o l d e f i n e d b y N V C R
D e v i c e f u l l y a c c e s s i b l e
W IP = 0
W E L = 0
Figure 135.:
N25Q256 - 3 V
t im e