n25q256 Numonyx, n25q256 Datasheet - Page 129

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n25q256

Manufacturer Part Number
n25q256
Description
256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
Manufacturer
Numonyx
Datasheet

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N25Q256 - 3 V
9.2.25
9.2.26
Read Volatile Enhanced Configuration Register, Dual I/O
The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the
Volatile Configuration Register to be read.
Figure 88. Read Volatile Enhanced Configuration Register instruction sequence
Write Volatile Enhanced Configuration Register, Dual I/O
The Write Volatile Enhanced Configuration Register instruction allows new values to be
written to the Volatile Enhanced Configuration register. Before it can be accepted, a write
enable (WREN) instruction must previously have been executed.
Apart form the parallelizing of the instruction code and the input data on the two pins DQ0
and DQ1, the instruction functionality is exactly the same as the Write Volatile Enhanced
Configuration Register (WRVECR) instruction of the Extended SPI protocol, please refer to
Section 9.1.40: Write Volatile Enhanced Configuration Register
Figure 89. Write Volatile Enhanced Configuration Register Instruction Sequence,
DQ0
DQ1
DIO-SPI
Dual I/O
DQ0
DQ1
C
S
C
S
0
Instruction
0
1
Instruction
2
1
3
2
7
6
4
Configuration Register Out
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
5
4
5
Byte
Volatile Enhanced
7
6
4
3
2
6
Configuration Register In
5
4
1
0
5
Byte
7
Volatile Enhanced
7
3
6
2
8
6
5
4
9 10 11
1
0
7
Byte
3
2
1
0
©2010 Micron Technology, Inc. All rights reserved.
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Instructions
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