n25q256 Numonyx, n25q256 Datasheet - Page 12

• Manufacturer Part Number: n25q256
• Description: 256-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

List of figures
N25Q256 - 3 V
Figure 101. Quad Command Fast Read using 4 Byte Address Instruction QSP, 6Ch . . . . . . . . . . . . 140
Figure 102. Quad Command Fast Read using 4 Byte Address Instruction QSP, ECh . . . . . . . . . . . . 141
Figure 103. Read OTP instruction and data-out sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 104. Write Enable instruction sequence QIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 105. Write Disable instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 106. Quad Command Page Program instruction sequence QIO-SPI, 02h. . . . . . . . . . . . . . . . 144
Figure 107. Quad Command Page Program instruction sequence QIO-SPI, 12h. . . . . . . . . . . . . . . . 144
Figure 108. Quad Command Page Program instruction sequence QIO-SPI, 32h. . . . . . . . . . . . . . . . 145
Figure 109. Program OTP instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 110. Subsector Erase instruction sequence QIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 111. Sector Erase instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 112. Bulk Erase instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 113. Program/Erase Suspend instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 114. Program/Erase Resume instruction sequence QIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 115. Read Status Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 116. Write Status Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 117. Read Lock Register instruction and data-out sequence QIO-SPI . . . . . . . . . . . . . . . . . . 151
Figure 118. Write to Lock Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 119. Read Flag Status Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 120. Clear Flag Status Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 121. Read NV Configuration Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . 153
Figure 122. Write NV Configuration Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . 154
Figure 123. Read Volatile Configuration Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . 155
Figure 124. Write Volatile Configuration Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . 156
Figure 125. Read Volatile Enhanced Configuration Register instruction sequence QIO-SPI . . . . . . . 157
Figure 126. Write Volatile Enhanced Configuration Register instruction sequence QIO-SPI . . . . . . . 158
Figure 127. Read Extended Address Register Instruction Sequence, Quad I/O . . . . . . . . . . . . . . . . . 159
Figure 128. Write Extended Address Register Instruction Sequence, Quad I/O . . . . . . . . . . . . . . . . . 159
Figure 129. Enter 4-Byte Address Mode Instruction Sequence, Quad I/O . . . . . . . . . . . . . . . . . . . . . 160
Figure 130. Exit 4-Byte Address Mode Instruction Sequence, Quad I/O . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 131. Reset Enable and Reset Memory Instruction Sequence, Quad I/O . . . . . . . . . . . . . . . . . 161
Figure 132. Read functionality Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 133. XIP mode directly after power on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 134. XiP: enter by VCR 2/2 (QIOFR in normal SPI protocol example) . . . . . . . . . . . . . . . . . . . 166
Figure 135. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 136. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 137. Reset AC waveforms while a program or erase cycle is in progress . . . . . . . . . . . . . . . . 175
Figure 138. Reset Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 139. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 140. Write protect setup and hold timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . 177
Figure 141. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 142. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 143. VPP
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
H
Figure 144. VDFPN8 (MLP8) Very Thin Dual Flat Package 8 leads, 8×6x1 mm Drawing . . . . . . . . . 179
Figure 145. SO16 wide - 16-lead plastic small outline, 300 mils body width, Drawing . . . . . . . . . . . . 180
Figure 146. TBGA - 6 x 8 mm, 24-ball, mechanical package outline (Feasability Evaluation). . . . . . . 181
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