upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 102

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upd78f9211grt2-jjg-a

Manufacturer Part Number
upd78f9211grt2-jjg-a
Description
8-bit Single-chip Microcontrollers
Manufacturer
ETC-unknow
Datasheet
102
Note If the valid edge of TI000 is specified to be both the rising and falling edges, 16-bit timer capture/compare
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
Figure 6-24. Control Register Settings for Pulse Width Measurement with Free-Running Counter and
register 000 (CR000) cannot perform the capture operation. When the CRC001 bit value is 1, the TM00
count value is not captured in the CR000 register when a valid edge of the TI010 pin is detected, but the
input from the TI010 pin can be used as an external interrupt source because INTTM000 is generated at
that timing.
CRC00
PRM00
TMC00
See the description of the respective control registers for details.
ES110
0/1
7
0
7
0
ES100
0/1
6
0
6
0
Two Capture Registers (with Rising Edge Specified)
(c) 16-bit timer mode control register 00 (TMC00)
(a) Capture/compare control register 00 (CRC00)
ES010
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
5
0
0
5
0
(b) Prescaler mode register 00 (PRM00)
ES000
4
0
1
4
0
User’s Manual U16994EJ3V0UD
TMC003
3
0
3
0
0
TMC002
CRC002
1
2
0
1
TMC001
CRC001
PRM001
0/1
0/1
1
CRC000
OVF00
PRM000
0/1
1
0
Free-running mode
Selects count clock (setting “11” is prohibited).
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
CR000 used as capture register
Captures to CR000 at inverse edge
to valid edge of TI000
CR010 used as capture register
Note
.

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