upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 143

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

8.4.2
system clock.
1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).
operation in STOP mode and 8.4.4 Watchdog timer operation in HALT mode.
The operation clock of the watchdog timer can be selected as either the low-speed internal oscillation clock or
After reset is released, operation is started at the maximum cycle of the low-speed internal oscillation clock (bits 2,
The following shows the watchdog timer operation after reset release.
1.
2.
3.
Notes 1.
Caution In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution.
For the watchdog timer operation during STOP mode and HALT mode in each status, see 8.4.3 Watchdog timer
A status transition diagram is shown below.
The status after reset release is as follows.
• Operation clock: Low-speed internal oscillation clock
• Cycle: 2
• Counting starts
The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instruction
• Operation clock: Any of the following can be selected using bits 3 and 4 (WDCS3 and WDCS4).
• Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Watchdog timer operation when “low-speed internal oscillator can be stopped by software” is
selected by option byte
Low-speed internal oscillation clock
Syatem clock (f
Watchdog timer operation stopped
2.
3.
After HALT/STOP mode is released, counting is started again using the operation clock of the
watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter
is not cleared to 0 but holds its value.
As soon as WDTM is written, the counter of the watchdog timer is cleared.
Set bits 7, 6, and 5 to 0, 1, 1, respectively. Do not set the other values.
At the first write, If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and ×,
respectively, an internal reset signal is not generated even if the following processing is performed.
• WDTM is written a second time.
• A 1-bit memory manipulation instruction is executed to WDTE.
• A value other than ACH is written to WDTE.
Notes 1, 2, 3
18
/f
RL
(546.13 ms: At operation with f
.
X
)
CHAPTER 8 WATCHDOG TIMER
User’s Manual U16994EJ3V0UD
RL
= 480 kHz (MAX.))
143