upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 270

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

270
Note Only when rp = BC, DE, or HL.
Remark
MOVW
XCHW
ADD
ADDC
SUB
Mnemonic
One instruction clock cycle is one CPU clock cycle (f
(PCC).
rp, #word
AX, saddrp
saddrp, AX
AX, rp
rp, AX
AX, rp
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
Operand
Note
Note
Note
CHAPTER 17 INSTRUCTION SET OVERVIEW
Bytes
3
2
2
1
1
1
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
User’s Manual U16994EJ3V0UD
Clocks
6
6
8
4
4
8
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
(saddrp) ← AX
rp ← word
AX ← (saddrp)
AX ← rp
rp ← AX
AX ↔ rp
A, CY ← A + byte
(saddr), CY ← (saddr) + byte
A, CY ← A + r
A, CY ← A + (saddr)
A, CY ← A + (addr16)
A, CY ← A + (HL)
A, CY ← A + (HL + byte)
A, CY ← A + byte + CY
(saddr), CY ← (saddr) + byte + CY
A, CY ← A + r + CY
A, CY ← A + (saddr) + CY
A, CY ← A + (addr16) + CY
A, CY ← A + (HL) + CY
A, CY ← A + (HL + byte) + CY
A, CY ← A − byte
(saddr), CY ← (saddr) − byte
A, CY ← A − r
A, CY ← A − (saddr)
A, CY ← A − (addr16)
A, CY ← A − (HL)
A, CY ← A − (HL + byte)
CPU
) selected by the processor clock control register
Operation
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Flag
AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×