upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 341

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

A/D
converter
Interrupt
functions
Standby
Function
Function
Interrupt
request flag
(ADIF)
Conversion
results just after
A/D conversion
start
A/D conversion
result register
(ADCR,
ADCRH) read
operation
IF0: Interrupt
request flag
registers,
MK0: Interrupt
mask flag
registers
INTM0: External
interrupt mode
register 0
Interrupt
requests are
held pending
Interrupt
request pending
STOP mode
STOP mode,
HALT mode
STOP mode
OSTS:
Oscillation
stabilization
time select
register
Details of
Function
−
The interrupt request flag (ADIF) is not cleared even if the analog input channel
specification register (ADS) is changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D
conversion result and ADIF for the pre-change analog input may be set just
before the ADS rewrite. Caution is therefore required since, at this time, when
ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D
conversion for the post-change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D
conversion operation is resumed.
The first A/D conversion value immediately after A/D conversion starts may not
fall within the rating range if the ADCS bit is set to 1 within 1
was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures
such as polling the A/D conversion end interrupt request (INTAD) and removing
the first conversion result.
When a write operation is performed to the A/D converter mode register (ADM)
and analog input channel specification register (ADS), the contents of ADCR and
ADCRH may become undefined. Read the conversion result following conversion
completion before writing to ADM and ADS. Using a timing other than the above
may cause an incorrect conversion result to be read.
Because P21 and P32 have an alternate function as external interrupt inputs,
when the output level is changed by specifying the output mode of the port
function, an interrupt request flag is set. Therefore, the interrupt mask flag should
be set to 1 before using the output mode.
Be sure to clear bits 0, 1, 6, and 7 to 0.
Before setting the INTM0 register, be sure to set the corresponding interrupt mask
flag (××MK× = 1) to disable interrupts. After setting the INTM0 register, clear the
interrupt request flag (××IF× = 0), then clear the interrupt mask flag (××MK× = 0),
which will enable interrupts.
Interrupt requests will be held pending while the interrupt request flag registers
(IF0) or interrupt mask flag registers (MK0) are being accessed.
Multiple interrupts can be acknowledged even for low-priority interrupts.
The LSRSTOP setting is valid only when “Can be stopped by software” is set for
the low-speed internal oscillator by the option byte.
When shifting to the STOP mode, be sure to stop the peripheral hardware
operation before executing STOP instruction (except the peripheral hardware that
operates on the low-speed internal oscillation clock).
The following sequence is recommended for operating current reduction of the
A/D converter when the standby function is used: First clear bit 7 (ADCS) and bit
0 (ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D
conversion operation, and then execute the HALT or STOP instruction.
If the low-speed internal oscillator is operating before the STOP mode is set,
oscillation of the low-speed internal oscillation clock cannot be stopped in the
STOP mode (refer to Table 11-1).
To set and then release the STOP mode, set the oscillation stabilization time as
follows.
set by OSTS
Expected oscillation stabilization time of resonator ≤ Oscillation stabilization time
APPENDIX C LIST OF CAUTIONS
User’s Manual U16994EJ3V0UD
Cautions
µ
s after the ADCE bit
p. 164
p. 165
p. 165
pp. 169,
170
p. 170
p. 171
p. 173
p. 174
p. 176
p. 177
p. 177
p. 177
p. 178
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