upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 137

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

Notes 1. As long as power is being supplied, low-speed internal oscillator cannot be stopped (except in the reset
Watchdog timer clock
source
Operation after reset
Operation mode
selection
Features
Remarks 1. f
2. The conditions under which clock supply to the watchdog timer is stopped differ depending on the clock
period).
source of the watchdog timer.
<1> If the clock source is f
<2> If the clock source is f
2. f
• When f
• In HALT/STOP mode
• During oscillation stabilization time
• If the CPU clock is f
• In HALT/STOP mode
RL
X
: System clock oscillation frequency
: Low-speed internal oscillation clock oscillation frequency
Table 8-2. Option Byte Setting and Watchdog Timer Operation Mode
Fixed to f
Operation starts with the maximum interval (2
The interval can be changed only once.
The watchdog timer cannot be stopped.
Low-Speed Internal Oscillator Cannot Be Stopped Low-Speed Internal Oscillator Can Be Stopped by Software
X
is stopped
RL
Note 1
.
X
RL
X
, clock supply to the watchdog timer is stopped under the following conditions.
and if f
, clock supply to the watchdog timer is stopped under the following conditions.
CHAPTER 8 WATCHDOG TIMER
User’s Manual U16994EJ3V0UD
RL
is stopped by software before execution of the STOP instruction
Option Byte Setting
18
/f
RL
). Operation starts with the maximum interval
• Selectable by software (f
• When reset is released: f
(2
The clock selection/interval can be changed only
once.
The watchdog timer can be stopped
18
/f
RL
).
X
RL
, f
RL
or stopped)
Note 2
.
137