upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 336

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

336
16-bit
timer/
event
counters
00
Function
PRM00:
Prescaler mode
register 00
Interval timer
External event
counter
Pulse width
measurement
Square-wave
output
PPG output
Details of
Function
Always set data to PRM00 after stopping the timer operation.
If the valid edge of the TI000 pin is to be set as the count clock, do not set the
clear/start mode and the capture trigger at the valid edge of the TI000 pin.
In the following cases, note with caution that the valid edge of the TI0n0 pin is
detected.
<1> Immediately after a system reset, if a high level is input to the TI0n0 pin, the
operation of the 16-bit timer counter 00 (TM00) is enabled
→If the rising edge or both rising and falling edges are specified as the valid edge
<2> If the TM00 operation is stopped while the TI0n0 pin is high level, TM00
operation is then enabled after a low level is input to the TI0n0 pin
→If the falling edge or both rising and falling edges are specified as the valid
<3> If the TM00 operation is stopped while the TI0n0 pin is low level, TM00
operation is then enabled after a high level is input to the TI0n0 pin
→If the rising edge or both rising and falling edges are specified as the valid edge
The sampling clock used to eliminate noise differs when a TI000 valid edge is
used as the count clock and when it is used as a capture trigger. In the former
case, the count clock is f
prescaler mode register 00 (PRM00). The capture operation is not performed
until the valid edge is sampled and the valid level is detected twice, thus
eliminating noise with a short pulse width.
When using P21 as the input pin (TI010) of the valid edge, it cannot be used as a
timer output (TO00). When using P21 as the timer output pin (TO00), it cannot be
used as the input pin (TI010) of the valid edge.
change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter
00 (17) Changing compare register during timer operation.
When reading the external event counter count value, TM00 should be read.
To use two capture registers, set the TI000 and TI010 pins.
The measurable pulse width in this operation example is up to 1 cycle of the timer
counter.
Changing the CR000 setting during TM00 operation may cause a malfunction. To
change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter
00 (17) Changing compare register during timer operation.
Changing the CRC0n0 setting during TM00 operation may cause a malfunction.
To change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event
Counter 00 (17) Changing compare register during timer operation.
Values in the following range should be set in CR000 and CR010.
0000H < CR010 < CR000 ≤ FFFFH
Changing the CR000 setting during TM00 operation may cause a malfunction. To
of the TI0n0 pin, a rising edge is detected immediately after the TM00
operation is enabled.
edge of the TI0n0 pin, a falling edge is detected immediately after the TM00
operation is enabled.
of the TI0n0 pin, a rising edge is detected immediately after the TM00
operation is enabled.
APPENDIX C LIST OF CAUTIONS
User’s Manual U16994EJ3V0UD
XP
, and in the latter case the count clock is selected by
Cautions
99, 101,
103
pp. 90,
116
pp. 90,
118
pp. 91,
120
pp. 91,
120
pp. 91,
120
p. 92
pp. 96,
120
pp. 97,
118
pp. 97,
p. 105
p. 107
pp. 108,
120
Page
(4/14)