upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 108

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

108
Cautions 1. Values in the following range should be set in CR000 and CR010:
Remark ×: Don’t care
TOC00
PRM00
CRC00
TMC00
ES110
0/1
2. The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of
7
0
7
0
7
0
0000H < CR010 < CR000 ≤ FFFFH
(CR010 setting value + 1)/(CR000 setting value + 1).
OSPT00
ES100
0/1
0
6
0
6
0
Figure 6-30. Control Register Settings for PPG Output Operation
OSPE00
ES010
0/1
0
5
0
5
0
TOC004
ES000
(b) 16-bit timer output control register 00 (TOC00)
(d) 16-bit timer mode control register 00 (TMC00)
(a) Capture/compare control register 00 (CRC00)
0/1
1
4
0
4
0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
LVS00
(c) Prescaler mode register 00 (PRM00)
TMC003
0/1
3
0
3
0
1
LVR00
TMC002
CRC002
0/1
User’s Manual U16994EJ3V0UD
0
0
1
2
TOC001
TMC001
CRC001
PRM001
1
0/1
×
0
TOE00
CRC000
OVF00
PRM000
1
0/1
0
0
Enables TO00 output.
Inverts output on match between TM00 and CR000.
Specifies initial value of TO00 output F/F (setting "11" is prohibited).
Inverts output on match between TM00 and CR010.
Disables one-shot pulse output.
CR000 used as compare register
CR010 used as compare register
Clears and starts on match between TM00 and CR000.
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)