upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 77

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upd78f9211grt2-jjg-a

Manufacturer Part Number
upd78f9211grt2-jjg-a
Description
8-bit Single-chip Microcontrollers
Manufacturer
ETC-unknow
Datasheet
(3) External clock input circuit
Note Operation stop time is 277
If external clock input is selected by the option byte, the following is possible.
• High-speed operation
• Improvement of expandability
Figures 5-12 and 5-13 show the timing chart and status transition diagram of default start by external clock input.
(a) The internal reset signal is generated by the power-on clear function on power application, the option byte is
(b) The option byte is referenced and the system clock is selected. Then the external clock operates as the
The accuracy of processing is improved as compared with high-speed internal oscillation (8 MHz (TYP.))
because an oscillation frequency of 1 MHz to 10 MHz can be selected and an external clock with a small
frequency deviation can be supplied.
If the external clock input circuit is selected as the oscillator, the X2 pin can be used as an I/O port pin. For
details, refer to CHAPTER 4 PORT FUNCTIONS.
referenced after reset, and the system clock is selected.
system clock.
System clock
Internal reset
CPU clock
RESET
V
DD
H
Figure 5-12. Timing of Default Start by External Clock Input
(a)
µ
s (MIN.), 544
System clock is selected.
CHAPTER 5 CLOCK GENERATORS
(Operation stops
Option byte is read.
User’s Manual U16994EJ3V0UD
µ
s (TYP.), and 1.075 ms (MAX.).
Note
)
(b)
PCC = 02H, PPCC = 02H
External clock input
77

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