upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 172

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to
the PC, and execution branches.
the interrupt is acknowledged after the instruction under execution is complete. Figure 10-7 shows an example of the
interrupt request acknowledgment timing for an 8-bit data transfer instruction MOV A, r. Since this instruction is
executed for 4 clocks, if an interrupt occurs for 3 clocks after the instruction fetch starts, the interrupt acknowledgment
processing is performed after the MOV A, r instruction is executed.
172
Figure 10-6 shows the algorithm of interrupt request acknowledgment.
When a maskable interrupt request is acknowledged, the contents of the PSW and PC are saved to the stack in
To return from interrupt servicing, use the RETI instruction.
××IF:
××MK:
IE:
If an interrupt request flag (××IF) is set before an instruction clock n (n = 4 to 10) under execution becomes n − 1,
Interrupt
Clock
CPU
Interrupt request flag
Interrupt mask flag
Flag to control maskable interrupt request acknowledgment (1 = enable, 0 = disable)
Figure 10-7. Interrupt Request Acknowledgment Timing (Example of MOV A, r)
Figure 10-6. Interrupt Request Acknowledgment Processing Algorithm
No
MOV A, r
CHAPTER 10 INTERRUPT FUNCTIONS
Vectored interrupt
××MK = 0?
××IF = 1?
servicing
IE = 1?
Start
User’s Manual U16994EJ3V0UD
Yes (Interrupt request generated)
Yes
Yes
Saving PSW and PC, jump
No
No
to interrupt servicing
8 clocks
Interrupt request pending
Interrupt request pending
Interrupt servicing program