upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 226

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

226
(3) Flash status register (PFS)
1. Operating conditions of FPRERR flag
2. Operating conditions of VCERR flag
<Setting conditions>
<Reset conditions>
<Setting conditions>
• If PFCMD is written when the store instruction operation recently performed on a peripheral register is not to
• If the first store instruction operation after <1> is on a peripheral register other than FLPMC
• If the first store instruction operation after <2> is on a peripheral register other than FLPMC
• If a value other than the inverted value of the value to be set to FLPMC is written by the first store instruction
• If the first store instruction operation after <3> is on a peripheral register other than FLPMC
• If a value other than the value to be set to FLPMC (value written in <2>) is written by the first store instruction
• If 0 is written to the FPRERR flag
• If the reset signal is generation
• Erasure verification error
• Internal writing verification error
If data is not written to the flash programming mode control register (FLPMC), which is protected, in the correct
sequence (writing the flash protect command register (PFCMD)), FLPMC is not written and a protection error
occurs. If this happens, bit 0 of PFS (FPRERR) is set to 1.
When FPRERR is 1, it can be cleared to 0 by writing 0 to it.
Errors that may occur during self-programming are reflected in bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
VCERR or WEPRERR can be cleared by writing 0 to them.
All the flags of the PFS register must be pre-cleared to 0 to check if the operation is performed correctly.
PFS can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears PFS to 00H.
write a specific value (A5H) to FLPMC
after <2>
after <3>
Remark The numbers in angle brackets above correspond to the those in (2) Flash protect command
Address: FFA0H
Address: FFA1H
PFCMD
Symbol
Symbol
PFS
register (PFCMD).
Figure 16-13. Format of Flash Protect Command Register (PFCMD)
REG7
7
7
0
Figure 16-14. Format of Flash Status Register (PFS)
After reset: Undefined
After reset: 00H
REG6
6
6
0
CHAPTER 16 FLASH MEMORY
REG5
User’s Manual U16994EJ3V0UD
5
5
0
R/W
REG4
W
4
4
0
REG3
3
3
0
WEPRERR
REG2
2
2
VCERR
REG1
1
1
FPRERR
REG0
0
0