upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 215

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upd78f9211grt2-jjg-a

Manufacturer Part Number
upd78f9211grt2-jjg-a
Description
8-bit Single-chip Microcontrollers
Manufacturer
ETC-unknow
Datasheet
Note In the 78K0S/KY1+, the CLK and FLMD0 signals are connected to the X1 pin and the SI/RxD and SO/TxD
CLK
FLMD0
SI/RxD
SO/TxD
/RESET
V
GND
Pin Name
DGCLK
DGDATA
/RESET
V
GND
DD
Pin Name
DD
Note
signals to the X2 signal; therefore, these signals need to be directly connected.
Note
Note
Note
Output
Output
Input
Output
Output
Output
I/O
Output
I/O
I/O
FlashPro4 Connection Pin
Table 16-2. Wiring Between 78K0S/KY1+ and FlashPro4
PG-FPL2 Connection Pin
Table 16-3. Wiring Between 78K0S/KY1+ and PG-FPL2
Clock to 78K0S/KY1+
On-board mode signal
Receive signal
Receive signal/on-board mode signal
Reset signal
V
Ground
Clock to 78K0S/KY1+
Transmit/receive signal, on-board mode signal
Reset signal
V
Ground
DD
DGDATA
DD
Figure 16-4. Wiring diagram with FlashPro4
signal name
/RESET
signal name
/RESET
SO/TxD
DGCLK
FLMD0
Figure 16-5. Wiring diagram with PG-FPL2
SI/RxD
FlashPro4
voltage generation/voltage monitor
PG-FPL2
GND
GND
CLK
voltage generation
V
V
DD
DD
CHAPTER 16 FLASH MEMORY
User’s Manual U16994EJ3V0UD
Pin Function
Pin Function
78K0S/KY1+
1
2
3
4
5
6
7
8
78K0S/KY1+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
X1/P23/ANI3
X2/P22/ANI2
RESET/P34
V
V
9
16
15
14
13
12
11
10
9
DD
SS
X2/P22
RESET/P34
V
V
X1/P21
DD
SS
78K0S/KY1+ Connection Pin
78K0S/KY1+ Connection Pin
Pin Name
Pin Name
8
9
12
5
4
8
9
12
5
4
Pin No.
Pin No.
215

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