upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 243

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upd78f9211grt2-jjg-a

Manufacturer Part Number
upd78f9211grt2-jjg-a
Description
8-bit Single-chip Microcontrollers
Manufacturer
ETC-unknow
Datasheet
16.8.8 Example of byte write operation in self programming mode
An example of the byte write operation in self programming mode is explained below.
<1> Set 05H (byte write) to the flash program command register (FLCMD).
<2> Set the number of block to which data is to be written, to flash address pointer H (FLAPH).
<3> Set the address at which data is to be written, to flash address pointer L (FLAPL).
<4> Set the data to be written, to the flash write buffer register (FLW).
<5> Clear the flash status register (PFS).
<6> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)
<8> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
<9> Byte write processing is abnormally terminated.
<10> Byte write processing is normally terminated.
Note This setting is not required when the watchdog timer is not used.
Caution If a write results in failure, erase the block once and write to it again.
<7> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
Abnormal → <9>
Normal
HALT instruction if self programming has been executed.)
→ <10>
CHAPTER 16 FLASH MEMORY
User’s Manual U16994EJ3V0UD
Note
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